One of the more main achievements with Intel’s 18A is the utilization of BSPDN (Backside Power Delivery), which is said to move the power delivery process to the backside of the wafer. Intel’s 18A “high-density” versions are now said to report a macro bit density of 38.1 Mb/mm², and overall, things are looking pretty optimistic for the 18A process.
The 18A (1.8nm) chips will be the first productized chips with both PowerVia backside power delivery and RibbonFET gate-all-around (GAA) transistors. PowerVia provides optimized power routing to improve performance and transistor density. RibbonFET provides better transistor density along with faster transistor switching in a smaller area.
Intel is working to a broader foundry roadmap. There will be a follow-on 14A node which is Intel’s first to use High-NA EUV lithography. Numerous node extensions to other nodes will further expand Intel Foundry Services’ portfolio to a broader range of applications.
Brian Wang is a Futurist Thought Leader and a popular Science blogger with 1 million readers per month. His blog Nextbigfuture.com is ranked #1 Science News Blog. It covers many disruptive technology and trends including Space, Robotics, Artificial Intelligence, Medicine, Anti-aging Biotechnology, and Nanotechnology.
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